 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| CXD2467AQ Digital Signal Driver/Timing Generator Description The CXD2467AQ incorporates digital signal processor type RGB driver and timing generator functions onto a single IC. Operation is possible with a system clock up to 135MHz (max.). This IC can process video signals in bands up to SXGA standard, and can output the timing signals for driving various LCD panels such as SXGA (LCX028) and XGA (LCX017 and LCX023). Features * Various picture quality adjustment functions such as user adjustment, white balance adjustment and gamma correction * OSD MIX, black frame processing, mute and limiter functions * Drives various data projector LCD panels such as SXGA (LCX028) and XGA (LCX017 and LCX023) * Controls the sample-and-hold position of the CXA2112R sample-and-hold driver * Line inversion and field inversion signal generation * Supports AC drive of LCD panels during no signal Applications LCD projectors and other video equipment Structure Silicon gate CMOS IC Note) Company names and product names, etc. contained in these materials are the trademarks or registered trademarks of the respective companies. 240 pin QFP (Plastic) Absolute Maximum Ratings (VSS = 0V) * Supply voltage VDD VSS - 0.5 to +4.0 V * Input voltage VI Vss - 0.5 to VDD + 0.5 V * Output voltage VO Vss - 0.5 to VDD + 0.5 V * Storage temperature Tstg -55 to +125 C Recommended Operating Conditions * Supply voltage VDD 3.0 to 3.6 * Operating temperature Topr -20 to +75 V C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E99613-PS CXD2467AQ Block Diagram PSAVE1 PSAVE2 R, G, B IN R, G, B OSD YM YS 8x2x3 2x2x3 2 2 DSD 10 x 2 x 3 R, G, B OUT PCTL PCLK PDAT CLK2 CLK1P CLK1N CLK1C CLKSEL1 CLKPOL1 CLKSEL2 HDIN1 10 PARALLEL I/F CLKOUT HRET, ORACT, HST, HCK1, HCK2, DCK1, DCK1X, DCK2, DCK2X, ENB, PCG, CLP1, CLP2, VST, VCK, FRP, BLK, RGT, XRGT, DWN, HB, VB1, VB2, SHA, SHB, SHC, SHD, INV D Q Q TG HDPOL1 VDIN1 Direct Clear XCLR VDPOL1 CLK4 CLK3P CLK3N CLK3C CLKSEL3 CLKPOL2 CLKSEL4 HDIN2 D Q Q IRACT IRRET, IRACT HDPOL2 -2- CXD2467AQ Pin Configuration R1OUT9 R1OUT8 R1OUT7 R1OUT6 R1OUT5 R1OUT4 PSAVE1 ORACT TEST4 TEST3 TEST2 TEST1 IRACT R1IN1 R1IN2 R1IN3 R1IN4 R1IN5 DCK1X DCK2 DCK1 VDD VSS VSS 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 R1IN0 181 R2IN7 182 R2IN6 183 R2IN5 184 R2IN4 185 VDD 186 VSS 187 R2IN3 188 R2IN2 189 R2IN1 190 R2IN0 191 G1IN7 192 G1IN6 193 G1IN5 194 G1IN4 195 G1IN3 196 G1IN2 197 VSS 198 G1IN1 199 G1IN0 200 G2IN7 201 G2IN6 202 G2IN5 203 G2IN4 204 G2IN3 205 G2IN2 206 G2IN1 207 G2IN0 208 VDD 209 VSS 210 B1IN7 211 B1IN6 212 B1IN5 213 B1IN4 214 B1IN3 215 B1IN2 216 B1IN1 217 B1IN0 218 B2IN7 219 B2IN6 220 B2IN5 221 VSS 222 B2IN4 223 B2IN3 224 B2IN2 225 B2IN1 226 B2IN0 227 R1OSD1 228 R1OSD0 229 G1OSD1 230 G1OSD0 231 B1OSD1 232 B1OSD0 233 VDD 234 VSS 235 YM1 236 YS1 237 R2OSD1 238 R2OSD0 239 G2OSD1 240 VSS R1OUT3 120 R1OUT2 119 R1OUT1 118 R1OUT0 117 R2OUT9 116 R2OUT8 115 VSS 114 VDD 113 R2OUT7 112 R2OUT6 111 R2OUT5 110 R2OUT4 109 R2OUT3 108 VSS 107 R2OUT2 106 R2OUT1 105 R2OUT0 104 G1OUT9 103 G1OUT8 102 VSS 101 G1OUT7 100 G1OUT6 99 G1OUT5 98 G1OUT4 97 G1OUT3 96 VSS 95 G1OUT2 94 G1OUT1 93 G1OUT0 92 G2OUT9 91 G2OUT8 90 VSS 89 VDD 88 G2OUT7 87 G2OUT6 86 G2OUT5 85 G2OUT4 84 G2OUT3 83 VSS 82 G2OUT2 81 G2OUT1 80 G2OUT0 79 B1OUT9 78 VSS 77 B1OUT8 76 B1OUT7 75 B1OUT6 74 B1OUT5 73 B1OUT4 72 VSS 71 B1OUT3 70 B1OUT2 69 B1OUT1 68 B1OUT0 67 VSS 66 VDD 65 B2OUT9 64 B2OUT8 63 B2OUT7 62 B2OUT6 61 B2OUT5 B2OUT4 PSAVE2 DCK2X R1IN6 R1IN7 XRGT HCK2 HCK1 CLP2 CLP1 DWN PRG PCG SHD SHC RGT SHB SHA ENB VCK HST FRP VST BLK VB1 VB2 VDD VDD VDD 1 G2OSD0 2 B2OSD1 3 B2OSD0 4 YM2 5 YS2 6 VDD 7 VSS 8 PCTL 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 HDPOL1 PDAT9 VDD VSS PDAT1 VSS CLK1C VSS CLK2 VSS VSS CLKSEL1 CLK3N VDD VSS CLK3C VSS CLK4 CLKSEL3 VSS XCLR VDD VSS CLKSEL2 CLKSEL4 B2OUT0 PCLK PDAT8 PDAT0 CLKOUT CLKPOL1 CLKPOL2 B2OUT1 PDAT7 HDIN1 B2OUT2 PDAT6 VDIN1 HDIN2 IRRET VDPOL1 HDPOL2 B2OUT3 PDAT5 PDAT4 CLK1P CLK1N CLK3P PDAT3 PDAT2 HRET -3- VDD VSS VSS VSS INV HB CXD2467AQ Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol G2OSD0 B2OSD1 B2OSD0 YM2 YS2 VDD VSS PCTL PCLK PDAT9 PDAT8 PDAT7 PDAT6 PDAT5 PDAT4 PDAT3 PDAT2 VDD VSS PDAT1 PDAT0 HDIN1 VDIN1 HDPOL1 VDPOL1 CLK1P CLK1N VSS CLK1C VSS CLK2 VSS I/O I I I I I -- -- I I I I I I I I I I -- -- I I I I I I I I -- I -- I -- Description OSD green data input (port 2) OSD blue data input (port 2) OSD blue data input (port 2) OSD YM input (port 2) OSD YS input (port 2) Power supply GND Parallel I/F control signal input Parallel I/F clock input Parallel I/F data input Parallel I/F data input Parallel I/F data input Parallel I/F data input Parallel I/F data input Parallel I/F data input Parallel I/F data input Parallel I/F data input Power supply GND Parallel I/F data input Parallel I/F data input Horizontal sync signal input-1 Vertical sync signal input-1 HDIN1 input polarity selection (High: positive polarity, Low: negative polarity) VDIN1 input polarity selection (High: positive polarity, Low: negative polarity) Clock input-1 (small-amplitude differential input, positive polarity) Clock input-1 (small-amplitude differential input, negative polarity) GND Clock input-1 (CMOS input) GND 1/2 frequency-divided clock input-1 (CMOS input) GND -4- Input pin processing for open status -- -- -- L L -- -- H -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L L -- -- -- -- -- -- -- CXD2467AQ Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 Symbol CLKOUT Vss CLKSEL1 CLKSEL2 CLKPOL1 HDIN2 HDPOL2 CLK3P CLK3N VDD VSS CLK3C VSS CLK4 CLKSEL3 CLKSEL4 CLKPOL2 IRRET HRET VSS XCLR VDD VSS B2OUT0 B2OUT1 B2OUT2 B2OUT3 B2OUT4 B2OUT5 B2OUT6 B2OUT7 B2OUT8 B2OUT9 I/O O -- I I I I I I I -- -- I -- I I I I O O -- I -- -- O O O O O O O O O O Description 1/2 frequency-divided clock output GND Input clock selection (High: CLK1C, Low: CLK1P, N) Input clock selection (High: CLK2, Low: CLK1) 1/2 frequency division circuit output selection (High: XQ output, Low: Q output) Horizontal sync signal input-2 HDIN2 input polarity selection (High: positive polarity, Low: negative polarity) Clock input-2 (small-amplitude differential input, positive polarity) Clock input-2 (small-amplitude differential input, negative polarity) Power supply GND Clock input-2 (CMOS input) GND 1/2 frequency-divided clock input-2 (CMOS input) Input clock selection (High: CLK3C, Low: CLK3P, N) Input clock selection (High: CLK4, Low: CLK3) 1/2 frequency division circuit output selection (High: XQ output, Low: Q output) Auxiliary pulse output Auxiliary pulse output GND External clear (Low: reset) Power supply GND Blue data output (port 2) Blue data output (port 2) Blue data output (port 2) Blue data output (port 2) Blue data output (port 2) Blue data output (port 2) Blue data output (port 2) Blue data output (port 2) Blue data output (port 2) Blue data output (port 2) -5- Input pin processing for open status -- -- L L L -- L -- -- -- -- -- -- -- L L L -- -- -- H -- -- -- -- -- -- -- -- -- -- -- -- CXD2467AQ Pin No. 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol VDD Vss B1OUT0 B1OUT1 B1OUT2 B1OUT3 VSS B1OUT4 B1OUT5 B1OUT6 B1OUT7 B1OUT8 VSS B1OUT9 G2OUT0 G2OUT1 G2OUT2 VSS G2OUT3 G2OUT4 G2OUT5 G2OUT6 G2OUT7 VDD VSS G2OUT8 G2OUT9 G1OUT0 G1OUT1 G1OUT2 VSS G1OUT3 G1OUT4 G1OUT5 G1OUT6 I/O -- -- O O O O -- O O O O O -- O O O O -- O O O O O -- -- O O O O O -- O O O O Power supply GND Blue data output (port 1) Blue data output (port 1) Blue data output (port 1) Blue data output (port 1) GND Blue data output (port 1) Blue data output (port 1) Blue data output (port 1) Blue data output (port 1) Blue data output (port 1) GND Blue data output (port 1) Description Input pin processing for open status -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Green data output (port 2) Green data output (port 2) Green data output (port 2) GND Green data output (port 2) Green data output (port 2) Green data output (port 2) Green data output (port 2) Green data output (port 2) Power supply GND Green data output (port 2) Green data output (port 2) Green data output (port 1) Green data output (port 1) Green data output (port 1) GND Green data output (port 1) Green data output (port 1) Green data output (port 1) Green data output (port 1) -6- CXD2467AQ Pin No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 Symbol G1OUT7 VSS G1OUT8 G1OUT9 R2OUT0 R2OUT1 R2OUT2 VSS R2OUT3 R2OUT4 R2OUT5 R2OUT6 R2OUT7 VDD VSS R2OUT8 R2OUT9 R1OUT0 R1OUT1 R1OUT2 R1OUT3 R1OUT4 R1OUT5 R1OUT6 R1OUT7 VDD VSS R1OUT8 R1OUT9 PCG VB2 VB1 VSS HB DWN I/O O -- O O O O O -- O O O O O -- -- O O O O O O O O O O -- -- O O O O O -- O O Description Green data output (port 1) GND Green data output (port 1) Green data output (port 1) Red data output (port 2) Red data output (port 2) Red data output (port 2) GND Red data output (port 2) Red data output (port 2) Red data output (port 2) Red data output (port 2) Red data output (port 2) Power supply GND Red data output (port 2) Red data output (port 2) Red data output (port 1) Red data output (port 1) Red data output (port 1) Red data output (port 1) Red data output (port 1) Red data output (port 1) Red data output (port 1) Red data output (port 1) Power supply GND Red data output (port 1) Red data output (port 1) PCG pulse output VB2 signal output VB1 signal output GND HB signal output Up/down inversion signal output -7- Input pin processing for open status -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CXD2467AQ Pin No. 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 Symbol VST VCK VDD VSS ENB BLK HCK1 HCK2 VDD DCK1 DCK1X DCK2 DCK2X HST VSS RGT XRGT FRP PRG CLP1 CLP2 SHA SHB SHC SHD INV VDD VSS IRACT ORACT TEST1 TEST2 TEST3 TEST4 PSAVE1 I/O O O -- -- O O O O -- O O O O O -- O O O O O O O O O O O -- -- O O -- -- -- -- I V start pulse output V clock pulse output Power supply GND ENB pulse output BLK pulse output H clock pulse output 1 Description Input pin processing for open status -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L H clock pulse output 2 (reversed phase) Power supply Auxiliary pulse output Auxiliary pulse output Auxiliary pulse output Auxiliary pulse output H start pulse output GND Left/right inversion signal output Left/right inversion signal output (reversed polarity) AC drive inversion pulse output PRG pulse output Pedestal clamp pulse output 1 Pedestal clamp pulse output 2 External sample-and-hold driver control signal output External sample-and-hold driver control signal output External sample-and-hold driver control signal output External sample-and-hold driver control signal output External sample-and-hold driver control signal output Power supply GND Auxiliary pulse output Auxiliary pulse output Test pin (Connect to GND.) Test pin (Connect to GND.) Test pin (Connect to VDD.) Test pin (Connect to VDD.) Power saving pin (High: standby status, Low: normal status) -8- CXD2467AQ Pin No. 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 Symbol PSAVE2 R1IN7 R1IN6 VDD VSS R1IN5 R1IN4 R1IN3 R1IN2 R1IN1 R1IN0 R2IN7 R2IN6 R2IN5 R2IN4 VDD VSS R2IN3 R2IN2 R2IN1 R2IN0 G1IN7 G1IN6 G1IN5 G1IN4 G1IN3 G1IN2 VSS G1IN1 G1IN0 G2IN7 G2IN6 G2IN5 G2IN4 G2IN3 I/O I I I -- -- I I I I I I I I I I -- -- I I I I I I I I I I -- I I I I I I I Description Power saving pin (High: standby status, Low: normal status) Red data input (port 1) Red data input (port 1) Power supply GND Red data input (port 1) Red data input (port 1) Red data input (port 1) Red data input (port 1) Red data input (port 1) Red data input (port 1) Red data input (port 2) Red data input (port 2) Red data input (port 2) Red data input (port 2) Power supply GND Red data input (port 2) Red data input (port 2) Red data input (port 2) Red data input (port 2) Green data input (port 1) Green data input (port 1) Green data input (port 1) Green data input (port 1) Green data input (port 1) Green data input (port 1) GND Green data input (port 1) Green data input (port 1) Green data input (port 2) Green data input (port 2) Green data input (port 2) Green data input (port 2) Green data input (port 2) -9- Input pin processing for open status L -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CXD2467AQ Pin No. 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Symbol G2IN2 G2IN1 G2IN0 VDD VSS B1IN7 B1IN6 B1IN5 B1IN4 B1IN3 B1IN2 B1IN1 B1IN0 B2IN7 B2IN6 B2IN5 VSS B2IN4 B2IN3 B2IN2 B2IN1 B2IN0 R1OSD1 R1OSD0 G1OSD1 G1OSD0 B1OSD1 B1OSD0 VDD VSS YM1 YS1 R2OSD1 R2OSD0 G2OSD1 I/O I I I -- -- I I I I I I I I I I I -- I I I I I I I I I I I -- -- I I I I I Green data input (port 2) Green data input (port 2) Green data input (port 2) Power supply GND Blue data input (port 1) Blue data input (port 1) Blue data input (port 1) Blue data input (port 1) Blue data input (port 1) Blue data input (port 1) Blue data input (port 1) Blue data input (port 1) Blue data input (port 2) Blue data input (port 2) Blue data input (port 2) GND Blue data input (port 2) Blue data input (port 2) Blue data input (port 2) Blue data input (port 2) Blue data input (port 2) Description Input pin processing for open status -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- L L -- -- -- H: Pull-up, L: Pull-down OSD red data input (port 1) OSD red data input (port 1) OSD green data input (port 1) OSD green data input (port 1) OSD blue data input (port 1) OSD blue data input (port 1) Power supply GND OSD YM input (port 1) OSD YS input (port 1) OSD red data input (port 2) OSD red data input (port 2) OSD green data input (port 2) - 10 - CXD2467AQ Electrical Characteristics DC Characteristics Item Symbol Applicable pins -- CLK1C, CLK2 CLK3C, CLK4 1 Conditions -- CMOS input cell CMOS Schmitt trigger input cell (VSS = 0V, Topr = -20 to +75C) Min. 3.0 0.65VDD VSS 0.8VDD VSS (VDD x 0.606) - 0.1 VIL3 + 0.3 VSS All output pins -- -- CLK = 135MHz VDD = 3.3V Output load = 30pF 3 VDD - 0.5 VSS Typ. 3.3 -- -- -- -- VDD x 0.606 -- -- -- -- Max. 3.6 VDD + 0.3 0.25VDD VDD + 0.3 0.2VDD (VDD x 0.606) + 0.1 VDD VIH3 - 0.3 VDD 0.4 490 360 V Unit Supply voltage VDD Input voltage 1 Input voltage 2 VIH1 VIL1 VIH2 VIL2 VC (center level) VIH32 VIL32 Output voltage VOH VOL Input voltage 3 CLK1P, CLK1N CLK3P, CLK3N Small-amplitude differential input Current IDD consumption -- -- -- mA 1 Input pins other than those indicated in items Input voltage 1 and Input voltage 3. 2 VIH3 > (Maximum VC value) and VIL3 < (Minimum VC value). 3 PSAVE1 = PSAVE2 = H AC Characteristics Item Clock input cycle Input setup time Input hold time Output rise/fall delay time Output rise/fall delay time Output rise/fall delay time Output rise/fall delay time Cross-point time difference Cross-point time difference tis tih tor/tof tor/tof tor/tof tor/tof t t Symbol -- Applicable pins CLK1, CLK3 CLK2, CLK4 4 4 (VDD = 3.3 0.3V, VSS = 0V, Topr = -20 to +75C) Conditions -- -- -- -- Min. 7.4 14.8 3.5 1.5 9 9 8 9 -5 48 Typ. -- -- -- -- 12 12 11 12 -- 50 Max. -- -- -- -- 19 19 18 19 5 52 ns Unit HCK1, HCK2, HST CL = 90pF PCG, VST, VCK, ENB, BLK CLKOUT All other output pins HCK1, HCK2 HCK1, HCK2 CL = 50pF CL = 50pF CL = 30pF CL = 90pF CL = 90pF 4 RGB input, OSD input, HDIN1, HDIN2, VDIN - 11 - CXD2467AQ Timing Definition CLK1P, CLK3P 50% VIH3 VIL3 VIH3 CLK1N, CLK3N 50% VIL3 VDD CLK1C, CLK3C 50% 0V VDD CLK2, CLK4 50% 0V RGB input, OSD input HDIN1, HDIN2, VDIN1 VDD 50% tis tih 50% 0V CLK1P, CLK3P VIH3 50% 50% VIL3 VIH3 CLK1N, CLK3N 50% 50% VIL3 VDD CLK1C, CLK3C 50% 50% 0V VDD CLK2, CLK4 50% 50% 0V VDD CLKOUT tor 50% tof 50% tor 50% tof 50% 0V VDD Outputs other than CLKOUT 0V VDD Outputs other than CLKOUT 0V VDD HCK1 HCK2 t 50% 50% 0V VDD 50% t 50% 0V VDD HCK1, HCK2 50% th 50% tl 50% 0V - 12 - CXD2467AQ Parallel Transfer Data AC Characteristics Item PCTL setup time with respect to rise of PCLK PCTL hold time with respect to rise of PCLK PDAT[9:0] setup time with respect to rise of PCLK PDAT[9:0] hold time with respect to rise of PCLK PCLK pulse width (VDD = 3.3 0.3V, VSS = 0V, Topr = -20 to +75C) Symbol tcs tch tds tdh tw Min. 8T5 8T 4T 4T 4T Typ. -- -- -- -- -- Max. -- -- -- -- -- 5 T: Master clock (CLK1P/CLK1N, CLK1C, CLK3P/CLK3N, CLK3C) cycle [ns] Timing Definition tcs PCTL 50% tw PCLK 50% tds PDAT[9:0] 50% tdh tw tch VDD 50% 0V VDD 50% 0V VDD 50% 0V - 13 - CXD2467AQ Description of Operation 1. DSD and TG Blocks 1-1. Description of Input/Output Pins (a) Sync signal input pins (HDIN1 and VDIN1) Horizontal and vertical separate sync signals are input to HDIN1 (Pin 22) and VDIN1 (Pin 23), respectively. The CXD2467AQ supports only non-interlace sync signals with a dot clock of 135MHz or less. Also, the HSYNC width should be 40 dot clocks or more, and the VSYNC width, 1H or more. (b) Sync signal polarity setting pins (HDPOL1 and VDPOL1) The polarity of the input horizontal and vertical sync signals are set by HDPOL1 (Pin 24) and VDPOL1 (Pin 25), respectively. Set to high level for positive polarity, and to low level for negative polarity. (c) Master clock input pins (CLK1P/CLK1N, CLK1C and CLK2) and clock selection pins (CLKSEL1 and CLKSEL2) Phase comparison is performed by an external circuit and a clock synchronized to the sync signal is input. The 1/N (N is the number of clocks during one horizontal period) frequency-divided dot clock pulse is output from HRET (Pin 51) for the external phase comparator. The master clock input pins consist of CLK1P/CLK1N (Pins 26 and 27) for small-amplitude differential input (center level: 2.0V, amplitude: 0.4V), and CLK1C (Pin 29) and CLK2 (Pin 31) for CMOS level input for a total of three channels. These are selected according to CLKSEL1 (Pin 35) and CLKSEL2 (Pin 36). CLKSEL1 L H -- CLKSEL2 L L H Selected clock input pins CLK1P/CLK1N (small-amplitude differential input, input at the same frequency as the dot clock) CLK1C (CMOS level input, input at the same frequency as the dot clock) CLK2 (CMOS level input, input at 1/2 the frequency of the dot clock) --: Don't care (d) Clock polarity switching pin (CLKPOL1) When CLK1P/1N or CLK1C is selected, the clock is 1/2 frequency divided inside the IC using the falling edge of the HD pulse as the reference. The polarity of this 1/2 frequency-divided clock is switched by CLKPOL1 (Pin 37). Normally CLKPOL1 is used at low level. CLK1P HDIN1 (Active Low) CLKPOL1 = L CLKPOL1 = H Internal clock for DSD and TG blocks (e) RGB signal input pins (R1IN, R2IN, G1IN, G2IN, B1IN and B2IN) These pins input RGB signals that have been demultiplexed to 1:2. The Red signal is input to R1IN (Pins 172, 173 and 176 to 181) and R2IN (Pins 182 to 185 and 188 to 191), the Green signal to G1IN (Pins 192 to 197, 199 and 200) and G2IN (Pins 201 to 208), and the Blue signal to B1IN (Pins 211 to 218) and B2IN (Pins 219 to 221 and 223 to 227). - 14 - CXD2467AQ (f) OSD signal input pins (R1OSD, R2OSD, G1OSD, G2OSD, B1OSD, B2OSD, YM1, YM2, YS1 and YS2) These pins input OSD signals that have been demultiplexed to 1:2. The Red signal is input to R1OSD (Pins 228 and 229) and R2OSD (Pins 238 and 239), the Green signal to G1OSD (Pins 230 and 231) and G2OSD (Pins 1 and 240), and the Blue signal to B1OSD (Pins 232 and 233) and B2OSD (Pins 2 and 3). In addition, the YM signal is input to YM1 (Pin 236) and YM2 (Pin 4), and the YS signal to YS1 (Pin 237) and YS2 (Pin 5). (g) Clock output pin (CLKOUT) The internal master clock is output from CLKOUT (Pin 33). (h) RGB signal output pins (R1OUT, R2OUT, G1OUT, G2OUT, B1OUT and B2OUT) These pins output the arithmetically processed RGB signals in the 1:2 demultiplexed state. The Red signal is output from R1OUT (Pins 118 to 125, 128 and 129) and R2OUT (Pins 105 to 107, 109 to 113, 116 and 117), the Green signal from G1OUT (Pins 93 to 95, 97 to 101, 103 and 104) and G2OUT (Pins 80 to 82, 84 to 88, 91 and 92), and the Blue signal from B1OUT (Pins 68 to 71, 73 to 77 and 79) and B2OUT (Pins 56 to 65). (i) Power saving pins (PSAVE1 and PSAVE2) The gamma block RAM can be set to standby mode using both PSAVE1 (Pin 170) and PSAVE2 (Pin 171). The RAM operates normally when these pins are set to low level, and enters standby mode to reduce power consumption when set to high level. At this time data can not be set to or read from the RAM. However, data set in advance in the RAM is held even in standby mode. In addition, the gamma block RAM output is the data held just before the pin voltage changes to high level, so the RAM output changes according to the data set in the RAM, etc. Therefore, using the mute function to fix the CXD2467AQ output to the desired level in standby mode is recommended. 1-2. RGB Signal and OSD Signal Pipeline Delay The RGB signal I/O pipeline delay is 42 dot clocks. In addition, the OSD, YM and YS signal pipeline delay is 12 dot clocks. Note that the phase relationship between each clock and the RGB signals is as shown in the figures below. This relationship is the same for the OSD, YM and YS signals. (1) CLK1P/CLK1N and CLK1C input (CLKPOL1 = low) HD (Active Low) CLK1P R1IN R2IN CLKOUT R1OUT R2OUT N - 44 N - 42 N - 40 N - 38 N - 36 N - 34 N - 32 N - 30 N - 28 N - 26 N - 24 N - 43 N - 41 N - 39 N - 37 N - 35 N - 33 N - 31 N - 29 N - 27 N - 25 N - 23 N-2 N-1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N + 8 N + 10 N+ 12 N + 14 N + 16 N + 18 N + 9 N + 11 N + 13 N + 15 N + 17 N + 19 - 15 - CXD2467AQ (2) CLK1P/CLK1N and CLK1C input (CLKPOL1 = high) HD (Active Low) CLK1P R1IN R2IN CLKOUT R1OUT R2OUT N - 44 N - 42 N - 40 N - 38 N - 36 N - 34 N - 32 N - 30 N - 28 N - 26 N - 24 N - 43 N - 41 N - 39 N - 37 N - 35 N - 33 N - 31 N - 29 N - 27 N - 25 N - 23 N-2 N-1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N + 8 N + 10 N+ 12 N + 14 N + 16 N + 18 N + 9 N + 11 N + 13 N + 15 N + 17 N + 19 (3) CLK2 input CLK2 R1IN R2IN CLKOUT R1OUT R2OUT N - 44 N - 42 N - 40 N - 38 N - 36 N - 34 N - 32 N - 30 N - 28 N - 26 N - 24 N - 43 N - 41 N - 39 N - 37 N - 35 N - 33 N - 31 N - 29 N - 27 N - 25 N - 23 N-2 N-1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N + 8 N + 10 N+ 12 N + 14 N + 16 N + 18 N + 9 N + 11 N + 13 N + 15 N + 17 N + 19 1-3. Description of DSD Block Signal Processing Functions The DSD block signal processing flow is shown below. The input RGB signals undergo fine picture quality adjustment in the order of user adjustment, white balance adjustment and gamma correction. Further, the CXD2467AQ is also equipped with various adjustment functions such as black frame processing, mute, OSD, limiter, and negative/positive inversion. White balance adjustment block User adjustment block Gamma correction block R, G, B IN USER GAIN USER BRIGHT SUB GAIN SUB BRIGHT GAMMA GAM GAIN GAM BRIGHT R, G, B OSD YS, YM BLACK FRAME Black frame processing block INVERT SELECT MUTE OSD LIMIT R, G, B OUT Mute block OSD block Limiter Negative/positive block inversion block - 16 - CXD2467AQ The various signal processing functions are described below. Note that the coefficients used for each arithmetic operation are set through the parallel I/F block. See the individual descriptions of each parallel I/F block item for a detailed description of the parallel I/F block. (a) User gain block This block performs multiplication processing as the user gain adjustment. Multiplication is performed as follows using the 8-bit data a[7:0] input to this IC and an 8-bit coefficient b[7:0]. c[15:0] = a[7:0] x b[7:0] The upper 12 bits c[15:4] of the arithmetic results are output. Next, the c[4] value is checked and rounding is performed to 11 bits. Further, the MSB of the rounded 11 bits is checked, clipping is performed to prevent overflow, and the lower 10 bits are output. Note that since the coefficient has 8 bits and the 5th bit of the arithmetic results is rounded, the maximum gain by this operation is 255/32 = 7.96875 times and this can be varied in 256 steps. The arithmetic coefficient is shared by R, G and B, and the initial value is 020h. Coefficient 8 b[7:0] Input a[7:0] 8 12 c[15:4] Rounding and clipping 10 axb Output (b) User bright block This block performs addition and subtraction processing as the user bright adjustment. The 10 bits of data a[9:0] output from the user gain block, a 10-bit coefficient b[9:0], and a 1-bit code are used as the inputs to perform arithmetic processing with an accuracy of 1 bit. Addition is performed when the code = 0, and subtraction when the code = 1. However, when performing subtraction, set an arithmetic coefficient that is the twos complement of the number to be subtracted. The initial adder performs the following addition: c[10:0] = a[9:0] + b[9:0] Then, overflow and underflow are judged according to c[10] which is the MSB of the arithmetic results and the code data value. 3FFh is output when overflow occurs, and 000h when underflow occurs. Note that the arithmetic coefficient and code are shared by R, G and B, and the initial values are 000h and 0h, respectively. Coefficient 10 b[9:0] 10 11 c[10:0] Code Input a[9:0] a+b Clipping 10 Output - 17 - CXD2467AQ (c) Sub gain block This block performs multiplication processing as the white balance gain adjustment. Multiplication is performed as follows using the 10-bit data a[9:0] output from the user bright block and an 8-bit coefficient b[7:0] as inputs. c[17:0] = a[9:0] x b[7:0] The upper 13 bits c[17:5] of the arithmetic results are output. Next, the c[5] value is checked and rounding is performed to 12 bits. Further, the upper 2 bits of the rounded 12 bits are checked, clipping is performed to prevent overflow, and the lower 10 bits are output. Note that since the coefficient has 8 bits and the 6th bit of the arithmetic results is rounded, the maximum gain by this operation is 255/64 = 3.984375 times and this can be varied in 256 steps. The arithmetic coefficients can be set independently for R, G and B, and the initial value is 040h for each. Coefficient 8 b[7:0] Input a[9:0] 10 13 c[17:5] Rounding and clipping 10 axb Output (d) Sub bright block This block performs addition and subtraction processing as the white balance bright adjustment. Note that the block configuration is the same as the user bright block. However, the arithmetic coefficients and codes can be set independently for R, G and B, and the initial values are 000h and 0h for each, respectively. (e) Gamma block This block performs gamma correction for the user- and white balance-adjusted signal. This block comprises a 10-bit x 1024-word RAM, and the gamma correction curve can be set as desired. The results of this correction are output as 10 bits. The RAM data is set through the parallel I/F block. Note that the RAM output is undetermined while data is being set in this RAM, and also during power-on. Input 10 RAM 10bit x 1024 word 10 Output (f) Gamma gain block This block performs multiplication processing for the gamma-corrected signal as the gain adjustment for correcting variance in the VT curve of the LCD panel. Multiplication is performed as follows using the 10-bit data a[9:0] output from the gamma block and an 8-bit coefficient b[7:0] as inputs. c[17:0] = a[9:0] x b[7:0] The upper 12 bits c[17:6] of the arithmetic results are output. Next, the c[6] value is checked and rounding is performed to 11 bits. Further, the MSB of the rounded 11 bits is checked, clipping is performed to prevent overflow, and the lower 10 bits are output. Note that since the coefficient has 8 bits and the 7th bit of the arithmetic results is rounded, the maximum gain by this operation is 255/128 = 1.9921875 times and this can be varied in 256 steps. The arithmetic coefficients can be set independently for R, G and B, and the initial value is 080h for each. - 18 - CXD2467AQ Coefficient 8 b[7:0] Rounding and clipping Input a[9:0] 10 axb 12 c[17:6] 10 Output (g) Gamma bright block This block performs addition and subtraction processing for the gamma-corrected signal as the bright adjustment for correcting variance in the VT curve of the LCD panel. Note that the block configuration is the same as the user bright block. However, the arithmetic coefficients and codes can be set independently for R, G and B, and the initial values are 000h and 0h for each, respectively. (h) Black frame block This block can perform processing to fix the blanking period of the video signal to the desired level regardless of the front-end signal processing results. This is effective when attempting to display a video signal which has been pixel-converted using a scan converter, etc., on a LCD panel or other display with a fixed number of pixels. If the number of pixels calculated from the effective period of the video signal to be displayed is less than the number of pixels of the display on which the signal is to be displayed, the blanking period of the video signal is displayed in the excess pixels. At this time, the displayed blanking period can be fixed to the desired level regardless of the gain and bright adjustment, gamma correction or other picture quality adjustment results by processing with this block. Here, the desired range of the video signal is replaced with 10-bit data (FRM) by switching the video signal (port 1 and port 2) and the coefficients using the pulse output from the pulse decoder. This range can be set as desired by the 11-bit coefficients (H1F, H2F, V1F and V2F) set in the pulse decoder. Then separate pulses are output from the pulse decoder for each of the port 1 (R1, G1 and B1) and port 2 (R2, G2 and B2) processing system blocks. By doing so, the black frame display range can be controlled in 1-dot units for the horizontal direction and in 1-line units for the vertical direction. Note that the 1-dot unit for the horizontal direction is the 1dot unit when viewed with the video signal displayed. Also, all coefficients are shared by R, G and B, and the initial value is 000h for each. However, note that when all black frame display range coefficients (H1F, H2F, V1F and V2F) are 000h, black frame display processing is not performed regardless of the black frame signal level coefficient values. 11 Internal HD Internal VD Internal MCLK Pulse decoder 11 11 11 Horizontal direction display range (H1F) Horizontal direction display range (H2F) Vertical direction display range (V1F) Vertical direction display range (V2F) Input (port 1) Coefficient (FRM) 10 10 Selector 10 Output (port 1) Input (port 2) 10 Selector 10 Output (port 2) - 19 - CXD2467AQ (i) Mute block This block performs mute processing by replacing the video signal with data of the desired level. Of the arithmetic coefficients set from the register, the mute data can be set independently for R, G and B, and the initial value is 000h for each. Also, the mute processing select data is shared by R, G and B, and the initial value is 1h. Therefore, mute is applied in the initial status. This is because the gamma block RAM output value is undetermined in the initial status. Therefore, note that in order to output the video signal, the mute processing select data must be set to 0h after data is set in the RAM. Select data 10 10 Selector Input Coefficient (mute level) 10 Output (j) OSD block This block performs video signal half-tone processing and OSD-MIX processing by inputting the 2-bit OSD data for each color and the YS and YM signals. In the initial shift block, the input data is shifted by one bit to the LSB side when the YM signal is high level. For example, when 0F0h is input, 078h is output. Video signal half-tone processing is performed in this manner by halving the input data level. The selector-1 block determines the OSD level by assigning four types of coefficients with respect to the OSD input data. In the Red block, R0D is selected and output when the OSD data is 0h, R1D when 1h, R2D when 2h, and R3D when 3h. Similarly, one of G0D, G1D, G2D or G3D is selected in the Green block, and one of B0D, B1D, B2D or B3D in the Blue block. Next, the selector-2 block performs OSD-MIX processing by switching the video signal and the data selected by the selector-1 block using the YS signal. Here, the selector-1 block output data is selected and OSD-MIX processing is performed when the YS signal is high level. The four coefficients can be set independently for R, G and B, and the initial values are all 000h. These coefficients are all 10 bits, and the OSD data is 2 bits for each of R, G and B, so 4 half tones can be selected as desired from among 1024 half tones for each of R, G and B. Therefore, the desired 64 (= 26) colors can be selected from among the total 1.07374 billion (= 230) colors for R, G and B. 2 10 10 10 10 Selector-1 10 OSD data Coefficient (R0D) Coefficient (R1D) Coefficient (R2D) Coefficient (R3D) YS signal YM signal Input 10 Shift 10 Selector-2 10 Output - 20 - CXD2467AQ (k) Limiter block This block performs limiter processing so that the output signal does not exceed a certain range. First, the input data is compared with the low-side limiter level LLIM and high-side limiter level HLIM coefficients. When these results are input data LLIM, the output is clipped at the LLIM level. When HLIM input data, the output is clipped at the HLIM level. When LLIM < IN < HLIM, the input data is output directly. Note that the two coefficients are shared by R, G and B, and the initial values are both 000h. Set the two coefficients so as to constantly maintain the relationship LLIM < HLIM. Also, when both coefficient values are 000h, limiter processing is not performed. Input Coefficient (HLIM) Coefficient (LLIM) 10 10 10 Limiter 10 Output (l) Negative/positive inversion This block performs negative/positive inversion processing. Here, negative/positive inversion processing is performed by outputting the input data directly when the select data is low, or inverting and outputting the input data when the select data is high. The select data is shared by R, G and B, and the initial value is 0h. Select data 10 Selector Input 10 Output - 21 - CXD2467AQ 2. IRACT Block The IRACT block consists of frequency divider and pulse generation circuits, and outputs a pulse synchronized with the horizontal sync signal input to HDIN2 from IRACT (Pin 164). The structure of this block is independent from other blocks in the CXD2467AQ. The clock system is also independent, so the IRACT block can be operated using a different clock than the TG and DSD blocks. (a) Sync signal input pin and signal polarity switching pin (HDIN2 and HDPOL2) The horizontal sync signal for the IRACT block is input to HDIN2 (Pin 38), and the sync signal polarity is set by HDPOL2 (Pin 39). Set HDPOL2 to high level when the horizontal sync signal is positive polarity, and to low level when negative polarity. (b) Clock input pins (CLK3P/CLK3N, CLK3C and CLK4) and clock selection pins (CLKSEL3 and CLKSEL4) These are the clock input pins for the IRACT block. Like the master clock, a clock synchronized to the horizontal sync signal is input. The 1/N (N is the number of clocks during one horizontal period) frequencydivided clock pulse is output from IRRET (Pin 50). Like the master clock, the clock input pins consist of CLK3P/CLK3N (Pins 40 and 41) for small-amplitude differential input (center level: 2.0V, amplitude: 0.4V), and CLK3C (Pin 44) and CLK4 (Pin 46) for CMOS level input for a total of three channels. These are selected according to CLKSEL3 (Pin 47) and CLKSEL4 (Pin 48). CLKSEL3 L H -- CLKSEL4 L L H Selected clock input pins CLK3P/CLK3N (small-amplitude differential input, input at the same frequency as the dot clock) CLK3C (CMOS level input, input at the same frequency as the dot clock) CLK4 (CMOS level input, input at 1/2 the frequency of the dot clock) --: Don't care (c) Clock polarity switching pin (CLKPOL2) When CLK3P/3N or CLK3C is selected, the clock is 1/2 frequency divided inside the IC using the falling edge of the HD pulse as the reference. The polarity of this 1/2 frequency-divided clock is switched by CLKPOL2 (Pin 49). Normally CLKPOL2 is used at low level. CLK3P HDIN2 (Active Low) CLKPOL2 = L CLKPOL2 = 2 Internal clock for IRACT block - 22 - CXD2467AQ 3. System Clear Pin (XCLR) All internal circuits are initialized by setting XCLR (Pin 53) low. Initialization should be performed during poweron. 4. Parallel I/F Block Register data settings in this IC are performed by parallel data. As shown in the Timing Chart below, the parallel I/F comprises a total 12-bit wide bus consisting of control signal PCTL (Pin 8), clock signal PCLK (Pin 9) and 10-bit wide data signal PDAT[9:0] (Pins 10 to 17, 20 and 21). The data signal is input in the order of main address, sub address and data. When setting data in this IC, divide the data into five blocks as shown in the table below. Next, the sub address specifies the initial address of the data to be written in the block designated by the main address. The data is set sequentially from the data at the address designated by the sub address. The address of each data set thereafter is automatically incremented by +1 from the address designated by the sub address, so further address setting is unnecessary. This makes it possible to set only the necessary data from the desired address of the desired block. Timing Chart PCTL (Pin 8) PCLK (Pin 9) PDAT[9:0] (Pins 10 to 17, 20 and 21) main sub address address data Main Address Table Main address 000h 001h 002h 003h 004h Set block Gamma block (Red) RAM Gamma block (Green) RAM Gamma block (Blue) RAM DSD arithmetic coefficients for other than gamma block TG and IRACT block setting data 4-1. Gamma Block (Main Address: 000h to 002h) In this block, the gamma correction data is set in a 10-bit x 1024-word RAM. Here, the set sub address directly becomes the RAM write address. Thereafter, the RAM write address is automatically incremented by +1. Following the main address, designate the RAM write start address in the sub address with 10 bits, then set the gamma correction data in 10 bits. - 23 - CXD2467AQ 4-2. DSD Block (Main Address: 003h) The DSD block data format is as follows. Data Format Sub address 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h 021h 022h 023h 024h 025h 026h 027h Data PDAT5 PDAT4 UG5 UG4 UB5 UB4 RSG5 RSG4 RSB5 RSB4 GSG5 GSG4 GSB5 GSB4 BSG5 BSG4 BSB5 BSB4 RGG5 RGG4 RGB5 RGB4 GGG5 GGG4 GGB5 GGB4 BGG5 BGG4 BGB5 BGB4 FRM5 FRM4 H1F5 H1F4 -- -- H2F5 H2F4 -- -- V1F5 V1F4 -- -- V2F5 V2F4 -- -- RM5 RM4 GM5 GM4 BM5 BM4 R0D5 R0D4 R1D5 R1D4 R2D5 R2D4 R3D5 R3D4 G0D5 G0D4 G1D5 G1D4 G2D5 G2D4 G3D5 G3D4 B0D5 B0D4 B1D5 B1D4 B2D5 B2D4 B3D5 B3D4 LLIM5 LLIM4 HLIM5 HLIM4 Initial value 020h 000h 040h 000h 040h 000h 040h 000h 080h 000h 080h 000h 080h 000h 000h 000h 000h 000h 000h 000h 000h 000h 004h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h 000h PDAT9 -- UB9 -- RSB9 -- GSB9 -- BSB9 -- RGB9 -- GGB9 -- BGB9 FRM9 H1F9 -- H2F9 -- V1F9 -- V2F9 -- RM9 GM9 BM9 R0D9 R1D9 R2D9 R3D9 G0D9 G1D9 G2D9 G3D9 B0D9 B1D9 B2D9 B3D9 LLIM9 HLIM9 PDAT8 UBF UB8 RSBF RSB8 GSBF GSB8 BSBF BSB8 RGBF RGB8 GGBF GGB8 BGBF BGB8 FRM8 H1F8 -- H2F8 -- V1F8 -- V2F8 -- RM8 GM8 BM8 R0D8 R1D8 R2D8 R3D8 G0D8 G1D8 G2D8 G3D8 B0D8 B1D8 B2D8 B3D8 LLIM8 HLIM8 PDAT7 UG7 UB7 RSG7 RSB7 GSG7 GSB7 BSG7 BSB7 RGG7 RGB7 GGG7 GGB7 BGG7 BGB7 FRM7 H1F7 -- H2F7 -- V1F7 -- V2F7 -- RM7 GM7 BM7 R0D7 R1D7 R2D7 R3D7 G0D7 G1D7 G2D7 G3D7 B0D7 B1D7 B2D7 B3D7 LLIM7 HLIM7 PDAT6 UG6 UB6 RSG6 RSB6 GSG6 GSB6 BSG6 BSB6 RGG6 RGB6 GGG6 GGB6 BGG6 BGB6 FRM6 H1F6 -- H2F6 -- V1F6 -- V2F6 -- RM6 GM6 BM6 R0D6 R1D6 R2D6 R3D6 G0D6 G1D6 G2D6 G3D6 B0D6 B1D6 B2D6 B3D6 LLIM6 HLIM6 PDAT3 UG3 UB3 RSG3 RSB3 GSG3 GSB3 BSG3 BSB3 RGG3 RGB3 GGG3 GGB3 BGG3 BGB3 FRM3 H1F3 -- H2F3 -- V1F3 -- V2F3 -- RM3 GM3 BM3 R0D3 R1D3 R2D3 R3D3 G0D3 G1D3 G2D3 G3D3 B0D3 B1D3 B2D3 B3D3 LLIM3 HLIM3 PDAT2 PDAT1 UG2 UG1 UB2 UB1 RSG2 RSG1 RSB2 RSB1 GSG2 GSG1 GSB2 GSB1 BSG2 BSG1 BSB2 BSB1 RGG2 RGG1 RGB2 RGB1 GGG2 GGG1 GGB2 GGB1 BGG2 BGG1 BGB2 BGB1 FRM2 FRM1 H1F2 H1F1 -- -- H2F2 H2F1 -- -- V1F2 V1F1 -- -- V2F2 V2F1 SMSEL INVSEL RM2 RM1 GM2 GM1 BM2 BM1 R0D2 R0D1 R1D2 R1D1 R2D2 R2D1 R3D2 R3D1 G0D2 G0D1 G1D2 G1D1 G2D2 G2D1 G3D2 G3D1 B0D2 B0D1 B1D2 B1D1 B2D2 B2D1 B3D2 B3D1 LLIM2 LLIM1 HLIM2 HLIM1 PDAT0 UG0 UB0 RSG0 RSB0 GSG0 GSB0 BSG0 BSB0 RGG0 RGB0 GGG0 GGB0 BGG0 BGB0 FRM0 H1F0 H1F10 H2F0 H2F10 V1F0 V1F10 V2F0 V2F10 RM0 GM0 BM0 R0D0 R1D0 R2D0 R3D0 G0D0 G1D0 G2D0 G3D0 B0D0 B1D0 B2D0 B3D0 LLIM0 HLIM0 --: Don't care - 24 - CXD2467AQ The detailed setting contents are described below. (a) UG: User gain block coefficient setting The user gain block arithmetic coefficient is set in UG7 (MSB) to UG0 (LSB). The initial value is 20h. (b) UB and UBF: User bright block coefficient settings The user bright block arithmetic coefficient is set in UB9 (MSB) to UB0 (LSB), and the code bit is set in UBF. Addition is performed when the code bit = 0, and subtraction when the code bit = 1. When performing subtraction, set an arithmetic coefficient that is the twos complement of the number to be subtracted. The initial values of the arithmetic coefficient and the code bit are 000h and 0h, respectively. (c) RSG, GSG and BSG: Sub gain block coefficient settings The R, G and B sub gain block arithmetic coefficients are set in RSG7 (MSB) to RSG0 (LSB), GSG7 (MSB) to GSG0 (LSB) and BSG7 (MSB) to BSG0 (LSB), respectively. The initial value of each coefficient is 40h. (d) RSB, RSBF, GSB, GSBF, BSB and BSBF: Sub bright block coefficient settings The R, G and B sub bright block arithmetic coefficients are set in RSB9 (MSB) to RSB0 (LSB), GSB9 (MSB) to GSB0 (LSB) and BSB9 (MSB) to BSB0 (LSB), respectively. Also, the R, G and B code bits are set in RSBF, GSBF and BSBF, respectively. Addition is performed when the code bit = 0, and subtraction when the code bit = 1. When performing subtraction, set an arithmetic coefficient that is the twos complement of the number to be subtracted. The initial values of the arithmetic coefficients and the code bits are 000h and 0h, respectively. (e) RGG, GGG and BGG: Gamma gain block coefficient settings The R, G and B gamma gain block arithmetic coefficients are set in RGG7 (MSB) to RGG0 (LSB), GGG7 (MSB) to GGG0 (LSB) and BGG7 (MSB) to BGG0 (LSB), respectively. The initial value of each coefficient is 80h. (f) RGB, RGBF, GGB, GGBF, BGB and BGBF: Gamma bright block coefficient settings The R, G and B gamma bright block arithmetic coefficients are set in RGB9 (MSB) to RGB0 (LSB), GGB9 (MSB) to GGB0 (LSB) and BGB9 (MSB) to BGB0 (LSB), respectively. Also, the R, G and B code bits are set in RGBF, GGBF and BGBF, respectively. Addition is performed when the code bit = 0, and subtraction when the code bit = 1. When performing subtraction, set an arithmetic coefficient that is the twos complement of the number to be subtracted. The initial values of the arithmetic coefficients and the code bits are 000h and 0h, respectively. (g) FRM, H1F, H2F, V1F and V2F: Black frame processing block coefficient settings The black frame signal level for the black frame processing block is set in FRM9 (MSB) to FRM0 (LSB). In addition, the black frame display range coefficients for the horizontal direction are set in H1F10 (MSB) to H1F0 (LSB) and H2F10 (MSB) to H2F0 (LSB), and for the vertical direction in V1F10 (MSB) to V1F0 (LSB) and V2F10 (MSB) to V2F0 (LSB). The horizontal direction display range can be set in 1-dot units using the HD input edge as the reference. The falling edge is used as the reference when HD input is negative polarity input, and the rising edge when positive polarity input. The vertical direction display range can be set in 1-line units using the VD input edge as the reference. The falling edge is used as the reference when VD input is negative polarity input, and the rising edge when positive polarity input. Set the display range values in H1F , H2F, V1F and V2F. Note that when all black frame display range coefficients are 000h, black frame processing is not performed. The initial value of each coefficient is 000h. - 25 - CXD2467AQ HD (Active Low) H1F H2F Black frame display range VD (Active Low) V1F V2F Black frame display range Black frame display range Black frame display range (h) SMSEL, RM, GM and BM: Mute block coefficient settings The mute processing select data for the R, G and B mute blocks is set in SMSEL. Also, the R, G and B mute level coefficients are set in RM9 (MSB) to RM0 (LSB), GM9 (MSB) to GM0 (LSB) and BM9 (MSB) to BM0 (LSB), respectively. Mute processing is performed when SMSEL = 1, and not when SMSEL = 0. The initial values of the select data and mute level coefficients are 1h and 000h, respectively. (i) R0D, R1D, R2D, R3D, G0D, G1D, G2D, G3D, B0D, B1D, B2D and B3D: OSD block coefficient settings The R, G and B OSD block decoding data is set in R0D9 (MSB) to R0D0 (LSB), R1D9 (MSB) to R1D0 (LSB), R2D9 (MSB) to R2D0 (LSB), R3D9 (MSB) to R3D0 (LSB), G0D9 (MSB) to G0D0 (LSB), G1D9 (MSB) to G1D0 (LSB), G2D9 (MSB) to G2D0 (LSB), G3D9 (MSB) to G3D0 (LSB), B0D9 (MSB) to B0D0 (LSB), B1D9 (MSB) to B1D0 (LSB), B2D9 (MSB) to B2D0 (LSB) and B3D9 (MSB) to B3D0 (LSB). The desired OSD color can be set by assigning the decoding data with respect to the input OSD data in the OSD block. The initial values are all 000h. (j) LLIM, HLIM: Limiter block coefficient settings The limiter block limit value data is set in LLIM9 (MSB) to LLIM0 (LSB) and HLIM9 (MSB) to HLIM0 (LSB). Be sure to set data so that the relationship LLIM < HLIM is constantly maintained. Note that when 000h is set for both LLIM and HLIM, limiter processing is not performed. The initial values are both 000h. (k) INVSEL: Negative/positive inversion block coefficient setting The negative/positive inversion block select data is set in INVSEL. Negative/positive inversion processing is performed when INVSEL = 1, and not when INVSEL = 0. The initial value is 0h, respectively. - 26 - CXD2467AQ 4-3. TG and IRACT Blocks (Main Address: 004h) The timing pulses output from the CXD2467AQ are generated according to the data set in the data register. The related registers are shown below. Sub addresses 000h to 025h are the TG block related data, and 026h to 02Bh are the IRACT block related data. The TG and IRACT block data format is as follows. Data Format Sub address 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h 021h 022h 023h 024h 025h 026h 027h 028h 029h 02Ah 02Bh Data PDAT9 PDAT8 PDAT7 PDAT6 PDAT5 PDAT4 PDAT3 PDAT2 PDAT1 PDAT0 PLP9 -- ORU9 -- ORD9 -- HP9 -- PCGU9 -- PCGD9 -- PRGU9 -- PRGD9 -- ENBU9 -- ENBD9 -- CP1U9 -- CP1D9 -- CP2U9 -- CP2D9 -- HSTU9 -- HSTD9 -- VCRV9 -- VP9 -- FRI9 -- IRP9 -- IRU9 -- IRD9 -- PLP8 SLVRS ORU8 -- ORD8 -- HP8 -- PCGU8 -- PCGD8 -- PRGU8 -- PRGD8 -- ENBU8 -- ENBD8 -- CP1U8 -- CP1D8 -- CP2U8 -- CP2D8 -- HSTU8 -- HSTD8 -- VCRV8 -- VP8 -- FRI8 SLDS IRP8 -- IRU8 -- IRD8 -- PLP4 PLP7 PLP5 PLP6 SLPRS3 SLPRS2 SLPRS1 SLPRS0 ORU7 ORU6 ORU5 ORU4 -- -- -- -- ORD7 ORD6 ORD5 ORD4 -- -- -- -- HP4 HP7 HP5 HP6 -- -- -- -- PCGU7 PCGU6 PCGU5 PCGU4 -- -- -- -- PCGD7 PCGD6 PCGD5 PCGD4 -- -- -- -- PRGU7 PRGU6 PRGU5 PRGU4 -- -- -- -- PRGD7 PRGD6 PRGD5 PRGD4 -- -- -- -- ENBU7 ENBU6 ENBU5 ENBU4 -- -- -- -- ENBD7 ENBD6 ENBD5 ENBD4 -- -- -- -- CP1U7 CP1U6 CP1U5 CP1U4 -- -- -- -- CP1D7 CP1D6 CP1D5 CP1D4 -- -- -- -- CP2U7 CP2U6 CP2U5 CP2U4 -- -- -- -- CP2D7 CP2D6 CP2D5 CP2D4 -- -- -- -- HSTU7 HSTU6 HSTU5 HSTU4 -- -- -- -- HSTD7 HSTD6 HSTD5 HSTD4 -- -- -- -- VCRV7 VCRV6 VCRV5 VCRV4 -- -- -- -- VP4 VP7 VP5 VP6 -- SLFR HSCN VSCN FRI4 FRI7 FRI5 FRI6 MBK1 MBK0 SHP0 SHP1 IRP4 IRP7 IRP5 IRP6 -- -- -- -- IRU4 IRU7 IRU5 IRU6 -- -- -- -- IRD4 IRD7 IRD5 IRD6 -- -- -- -- PLP3 SLHCK1 ORU3 -- ORD3 -- HP3 -- PCGU3 -- PCGD3 -- PRGU3 -- PRGD3 -- ENBU3 -- ENBD3 -- CP1U3 -- CP1D3 -- CP2U3 -- CP2D3 -- HSTU3 -- HSTD3 -- VCRV3 -- VP3 HB FRI3 SHP2 IRP3 -- IRU3 -- IRD3 -- PLP2 SLHCK0 ORU2 -- ORD2 -- HP2 -- PCGU2 -- PCGD2 -- PRGU2 -- PRGD2 -- ENBU2 -- ENBD2 -- CP1U2 -- CP1D2 -- CP2U2 -- CP2D2 -- HSTU2 -- HSTD2 -- VCRV2 -- VP2 VB1 FRI2 SHP3 IRP2 SLHR IRU2 -- IRD2 -- PLP1 PLP11 ORU1 ORU11 ORD1 ORD11 HP1 HP11 PCGU1 PCGU11 PCGD1 PCGD11 PRGU1 PRGU11 PRGD1 PRGD11 ENBU1 ENBU11 ENBD1 ENBD11 CP1U1 CP1U11 CP1D1 CP1D11 CP2U1 CP2U11 CP2D1 CP2D11 HSTU1 HSTU11 HSTD1 HSTD11 VCRV1 VCRV11 VP1 VB2 FRI1 INV IRP1 IRP11 IRU1 IRU11 IRD1 IRD11 PLP0 PLP10 ORU0 ORU10 ORD0 ORD10 HP0 HP10 PCGU0 PCGU10 PCGD0 PCGD10 PRGU0 PRGU10 PRGD0 PRGD10 ENBU0 ENBU10 ENBD0 ENBD10 CP1U0 CP1U10 CP1D0 CP1D10 CP2U0 CP2U10 CP2D0 CP2D10 HSTU0 HSTU10 HSTD0 HSTD10 VCRV0 VCRV10 VP0 VP10 FRI0 FRI10 IRP0 IRP10 IRU0 IRU10 IRD0 IRD10 Initial value 297h 015h 080h 000h 000h 000h 022h 000h 086h 000h 142h 000h 086h 000h 100h 000h 0FEh 000h 00Ch 000h 0C0h 000h 132h 000h 088h 000h 128h 000h 146h 000h 15Eh 000h 086h 000h 020h 02Eh 3FFh 001h 297h 001h 080h 000h 000h 000h --: Don't care - 27 - CXD2467AQ The detailed setting contents are described below. (a) PLP: PLL counter frequency division ratio setting This sets the frequency division ratio of the 1/N frequency divider (PLL counter) for phase comparison. The value of (total number of dots in one horizontal period N) - 1 is set in PLP11 (MSB) to PLP0 (LSB). The frequency division ratio can be set up to 4096. However, only even numbers can be set for the value of N. The initial value is 697h (N = 1688). (b) SLHCK: HCK cycle setting The HCK1 (Pin 142) and HCK2 (Pin 143) cycle is set in SLHCK1 (MSB) and SLHCK0 (LSB). 0h is set for LCD panels that perform 6-dot simultaneous sampling, 1h for 12-dot simultaneous sampling, 2h for 18-dot simultaneous sampling and 3h for 24-dot simultaneous sampling. Note that HCK2 is the reverse-phase signal of HCK1. The initial value is 1h (12-dot simultaneous sampling). (c) SLPRS: PLL counter reset cycle setting The PLL counter is reset according to the value set in PLP, but reset can also be applied separately by HSYNC. The HSYNC cycle at which reset is applied is set in SLPRS3 (MSB) to SLPRS0 (LSB). When 0h is set, the PLL counter is not reset. When 1h is set, the front edge of HSYNC is detected and the PLL counter is reset each time HSYNC is input. The reset cycle increases thereafter so that when Fh is set, the PLL counter is reset by HSYNC every 15H. The initial value is 1h (reset every 1H). (d) SLVRS: PLL counter VSYNC reset This sets whether to reset the PLL counter with each VSYNC. The PLL counter is not reset when set to 0h, and reset when 1h. However, when SLPRS = 0h (no reset by HSYNC), the PLL counter is not reset regardless of the SLVRS setting. The initial value is 0h (no reset). (e) ORU/ORD: ORACT pulse settings The ORACT (Pin 165) pulse rise position within one horizontal period is set in ORU11 (MSB) to ORU0 (LSB), and the fall position is set in ORD11 (MSB) to ORD0 (LSB). The PLL counter reset timing is used as the reference (all 0). Also, the least significant bit is ignored, so setting is in 2-dot units. The initial values are ORU = 080h and ORD = 000h. (f) HP: Picture horizontal position setting The timing at which the counter is initialized to generate the PCG (Pin 130), PRG (Pin 154), ENB (Pin 140), CLP1 (Pin 155), CLP2 (Pin 156), HST (Pin 149), HCK1 and HCK2 horizontal drive pulses within one horizontal period is set in HP11 (MSB) to HP0 (LSB). Changing this setting causes the phase relationships of the horizontal drive pulses as well as the changing positions of VCK (Pin 137) and FRP (Pin 153) relative to HSYNC to change in an interlocked manner, making it possible to change the picture horizontal position. Settings can be made in 1-dot units. Note that HCK1 and HCK2 are initialized at this timing, and change at the cycle set by SLHCK. (See the Timing Chart.) The initial value is 022h. (g) PCGU/PCGD, PRGU/PRGD, ENBU/ENBD, CP1U/CP1D, CP2U/CP2D and HSTU/HSTD: Horizontal drive pulse settings These set the rise and fall positions of the PCG, PRG, ENB, CLP1, CLP2 and HST pulses within one horizontal period. The horizontal drive pulse initialization timing set by HP is used as the reference. (See the Timing Chart.) Also, the least significant bit is ignored, so setting is in 2-dot units. The initial values are as follows. PCGU = 086h/PCGD = 142h PRGU = 086h/PRGD = 100h ENBU = 0FEh/ENBD = 00Ch CP1U = 0C0h/CP1D = 132h CP2U = 088h/CP2D = 128h HSTU = 146h/HSTD = 15Eh - 28 - CXD2467AQ (h) VCRV: VCK pulse polarity inversion position setting The VCK and FRP pulse polarity inversion position within one horizontal period is set in VCRV11 (MSB) to VCRV0 (LSB). The reference is the same as that for the horizontal drive pulse setting above. Also, the least significant bit is ignored, so setting is in 2-dot units. The initial value is 086h. (i) VP: Picture vertical position setting The picture vertical position is set in VP10 (MSB) to VP0 (LSB). Changing this setting causes the phase relationships of the VST (Pin 136), VCK and FRP pulses relative to VSYNC to change in an interlocked manner. Settings can be made in 1-line units. The initial value is 020h. (j) HB, VB1 and VB2: LCD panel control signal settings These set the LCD panel control signals. The data set in HB, VB1 and VB2 is output from the HB (Pin 134), VB1 (Pin 132) and VB2 (Pin 131) output pins, respectively. Also, when either VB1 or VB2 is set to 0h, the BLK pulse is output. The methods of using these signals differ according to the LCD panel, and some LCD panels may not even have input pins supporting these signals. See the specifications of the used LCD panel for details. The initial values are HB = 1h, VB1 = 1h and VB2 = 1h. (k) HSCN and VSCN: LCD panel scan direction settings These set the horizontal and vertical scan directions of the LCD panel. The HSCN setting data is output from RGT (Pin 151), and the VSCN setting data from DWN (Pin 135). Also, changing the HSCN setting reverses the HCK1 and HCK2 phases. See the specifications of the used LCD panel for a detailed description of the scan direction. The initial values are HSCN = 1h and VSCN = 0h. (l) SLFR: FRP pulse inversion cycle setting This sets the inversion cycle of the polarity inversion pulse (FRP pulse) used for AC driving of LCD panels. The polarity is inverted at 1-line cycles when set to 0h, and at 1-field cycles when set to 1h. The initial value is 0h (1-line inversion). (m) SHP0, SHP1, SHP2, SHP3 and INV: CXA2112R sample-and-hold control These control the sample-and-hold position of the CXA2112R (sample-and-hold driver). The SHP0, SHP1, SHP2 and SHP3 setting data is reflected to SHA, SHB, SHC and SHD (Pins 157 to 160) as shown below. Also, the INV setting data is output directly from the INV (Pin 161) output pin. See the specifications of the CXA2112R for a detailed description of control methods. The initial values are SHP0 = 0h, SHP1 = 0h, SHP2 = 0h, SHP3 = 0h and INV = 0h. Setting SHP3 to SHP0 0000 0001 0010 0011 0100 0101 0110 0111 SHPA L H Z Z L H Z Z Output SHPB L H L H L H L H SHPC L L L L H H H H SHPD L L L L H H H H Setting SHP3 to SHP0 1000 1001 1010 1011 1100 1101 1110 1111 SHPA L H Z Z L H Z Z Output SHPB L H L H L H L H SHPC Z Z Z Z Z Z Z Z SHPD L L L L H H H H Z: High impedance state - 29 - CXD2467AQ (n) FRI: Free-running cycle setting When VSYNC has not been input for a specified period, a judgment of "no signal" is made to allow AC driving of LCD panels even when there is no signal. In this case, a vertical start pulse and FRP pulse are output at a specified cycle (free-running operation). The period until a judgment of "no signal" is made and the VST pulse cycle during free-running operation are set in FRI10 (MSB) to FRI0 (LSB). The initial value is 7FFh (2048H cycle). (o) MBK0 and MBK1: Decimation operation settings This sets the decimation operation which decimates the display lines at a specified ratio. This IC has two builtin modes: 2/14-line decimation and 1/4-line decimation. MBK0 turns decimation operation on and off, and MBK1 selects the mode. Decimation is not performed when MBK0 = 0h, and is performed when MBK0 = 1h. Also, 2/14-line decimation is performed when MBK1 = 0h, and 1/4-line decimation when MBK1 = 1h. The initial values are MBK0 = 0h and MBK1 = 0h (no decimation). (p) SLDS: Test data This is test data. Set to 0h. The initial value is 0h. (q) IRP: IRACT block frequency divider frequency division ratio setting Like the PLL counter, this sets the frequency division ratio of the 1/N frequency divider for phase comparison. The value of (total number of dots in one horizontal period N) - 1 is set in IRP11 (MSB) to IRP0 (LSB). The frequency division ratio can be set up to 4096. However, only even numbers can be set for the value of N. The initial value is 697h (N = 1688). (r) SLHR: IRACT block frequency divider reset setting This sets whether the IRACT block frequency divider is reset by the HSYNC input to HDIN2. The frequency divider is reset when 0h, and not reset when 1h. The initial value is 0h (reset). (s) IRU/IRD: IRACT pulse settings The IRACT pulse rise position within one horizontal period is set in IRU11 (MSB) to IRU0 (LSB), and the fall position in IRD11 (MSB) to IRD0 (LSB) relative to the HSYNC input to HDIN2. The IRACT block frequency divider reset timing is used as the reference (all 0). Also, the least significant bit is ignored, so setting is in 2dot units. The initial values are IRU = 080h and IRD = 000h. Note) The above setting values may be invalid in certain cases. (For example, settings which exceed the number of clocks in 1H or number of lines in 1V of the input signal, etc.) Normal pulses will not be output in these cases, so be sure to refer to the setting examples on the following page when making the settings. - 30 - CXD2467AQ Data Register Setting Examples Examples of data register settings for typical LCD panels driven by this IC and input signals are shown below. The optimum settings may differ depending on the actual input signal specifications and differences in video signal processing systems, so be sure to adjust the setting values as necessary. (a) Example settings when using the LCX028 Input signal: SXGA (1280 x 1024 dots, fH = 64kHz, fV = 60Hz, dot clock = 108MHz) PLL counter H position PCG pulse PRG pulse ENB pulse CLP1 pulse HST pulse VCK/FRP inversion position V position PLP = 697h (N = 1688, same as default value) HP = 000h PCGU = 074h/PCGD = 136h PRGU = 074h/PRGD = 0F6h ENBU = 0F6h/ENBD = 008h CP1U = 088h/CP1D = 128h HSTU = 146h/HSTD = 15Eh VCRV = 074h VP = 020h (same as default value) (b) Example settings when using the LCX023 or LCX017 Input signal: XGA (1024 x 768 dots, fH = 48kHz, fV = 60Hz, dot clock = 65MHz) PLL counter H position PCG pulse PRG pulse ENB pulse CLP1 pulse HST pulse VCK/FRP inversion position V position Free-running frequency PLP = 53Fh (N = 1344) HP = 042h PCGU = 050h/PCGD = 0D4h PRGU = 050h/PRGD = 09Eh ENBU = 09Eh/ENBD = 002h CP1U = 024h/CP1D = 0B0h HSTU = 0CEh/HSTD = 0E6h VCRV = 050h VP = 023h FRI = 63Fh (1600H) - 31 - TG and IRACT Block Timing Chart Data register setting: Default (Example for input signal with total number of horizontal dots = 1688) Horizontal Direction Timing Chart 20-dot clocks (ck) (HDIN1) Horizontal drive pulse initialization position 128ck 194ck 114ck 138ck 160ck 24ck HRET 34ck ORACT CLP1 CLP2 HST HCK1 - 32 - 242ck 136ck 122ck 128ck HCK2 ENB 14ck PCG 4ck 188ck PRG VCK FRP (HDIN2) IRRET IRACT When HSCN = 0 (left/right inversion), the HCK1 and HCK2 phases are reversed. CXD2467AQ The 1H and 1V cycle FRP polarity is not specified. Vertical Direction Timing Chart Data register setting: Default (Example for input signal with total number of vertical lines = 1066) (HDIN1) (VDIN1) HRET ORACT VST VCK FRP - 33 - HST ENB PCG PRG BLK (HDIN2) IRRET IRACT CXD2467AQ The 1H and 1V cycle FRP polarity is not specified. Vertical Direction Timing Chart Data register setting: VB1 = 0 or VB2 = 0, VP = 01E/h, other settings = default (Example for input signal with total number of vertical lines = 1000) (HDIN1) (VDIN1) HRET ORACT VST VCK FRP - 34 - HST ENB PCG PRG BLK (HDIN2) IRRET IRACT CXD2467AQ The 1H and 1V cycle FRP polarity is not specified. Vertical Direction Timing Chart Data register setting: MBK0 = 1, MBK1 = 0, VP = 00A/h, other settings = default (Example for input signal with total number of vertical lines = 1250) (HDIN1) (VDIN1) HRET ORACT VST VCK FRP - 35 - HST ENB PCG PRG BLK (HDIN2) IRRET IRACT CXD2467AQ The 1H and 1V cycle FRP polarity is not specified. Vertical Direction Timing Chart Data register setting: MBK0 = 1, MBK1 = 1, VP = 00C/h, other settings = default (Example for input signal with total number of vertical lines = 1066) (HDIN1) (VDIN1) HRET ORACT VST VCK FRP - 36 - HST ENB PCG PRG BLK (HDIN2) IRRET IRACT CXD2467AQ The 1H and 1V cycle FRP polarity is not specified. CXD2467AQ Application Circuit To LCD panel From A/D converter 10 0.1 0.1 47k 47k 0.1 0.1 To D/A converter 0.1 10 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 VST DWN VCK DCK2X DCK1X DCK1 HST DCK2 HB R1OUT7 R1OUT6 R1OUT9 R1OUT8 R1OUT5 R1OUT4 R1OUT3 VDD VDD VDD VDD VB1 VB2 ORACT PSAVE2 PSAVE1 TEST4 TEST3 TEST2 TEST1 IRACT R1IN1 R1IN2 R1IN3 R1IN4 R1IN5 R1IN6 R1IN7 CLP2 CLP1 HCK2 HCK1 PRG XRGT PCG SHB SHA FRP BLK SHD SHC RGT ENB VDD INV VSS VSS VSS VSS VSS VSS R1 OUT2 120 R1OUT1 119 R1OUT0 118 R2OUT9 117 R2OUT8 116 VSS 115 VDD 114 R2OUT7 113 R2OUT6 112 R2OUT5 111 R2OUT4 110 R2OUT3 109 VSS 108 R2OUT2 107 R2OUT1 106 R2OUT0 105 G1OUT9 104 G1OUT8 103 VSS 102 G1OUT7 101 G1OUT6 100 G1OUT5 99 G1OUT4 98 G1OUT3 97 VSS 96 G1OUT2 95 G1OUT1 94 G1OUT0 93 G2OUT9 92 G2OUT8 91 VSS 90 VDD 89 G2OUT7 88 G2OUT6 87 G2OUT5 86 G2OUT4 85 G2OUT3 84 VSS 83 G2OUT2 82 G2OUT1 81 G2OUT0 80 B1OUT9 79 VSS 78 B1OUT8 77 B1OUT7 76 B1OUT6 75 B1OUT5 74 B1OUT4 73 VSS 72 B1OUT3 71 B1OUT2 70 B1OUT1 69 B1OUT0 68 VSS 67 VDD 66 B2OUT9 65 B2OUT8 64 B2OUT7 63 CLKPOL1 CLKPOL2 CLKSEL1 CLKSEL2 CLKSEL3 CLKSEL4 HDPOL1 CLKOUT HDPOL2 B2OSD1 B2OSD0 VDPOL1 B2OUT0 B2OUT1 B2OUT2 B2OUT3 CLK1N CLK1C CLK3N CLK3C CLK1P CLK3P PDAT9 PDAT8 PDAT7 PDAT6 PDAT5 PDAT4 PDAT3 PDAT2 PDAT1 PDAT0 HDIN2 HDIN1 IRRET VDIN1 B2OUT6 62 B2OUT5 61 B2 OUT4 0.1 0.1 To D/A converter 0.1 +3.3V 181 R1IN0 182 R2IN7 183 R2IN6 184 R2IN5 185 R2IN4 0.1 186 VDD 187 VSS 188 R2IN3 189 R2IN2 190 R2IN1 191 R2IN0 192 G1IN7 193 G1IN6 194 G1IN5 195 G1IN4 196 G1IN3 197 G1IN2 198 VSS 199 G1IN1 200 G1IN0 201 G2IN7 From A/D converter 202 G2IN6 203 G2IN5 204 G2IN4 205 G2IN3 206 G2IN2 207 G2IN1 208 G2IN0 0.1 209 VDD 210 VSS 211 B1IN7 212 B1IN6 213 B1IN5 214 B1IN4 215 B1IN3 216 B1IN2 217 B1IN1 218 B1IN0 219 B2IN7 220 B2IN6 221 B2IN5 222 VSS 223 B2IN4 224 B2IN3 225 B2IN2 226 B2IN1 227 B2IN0 228 R1OSD1 229 R1OSD0 230 G1OSD1 231 G1OSD0 232 B1OSD1 OSD input 233 B1OSD0 0.1 234 VDD 235 VSS 236 YM1 237 YS1 238 R2OSD1 239 R2OSD0 G2OSD1 240 G2 OSD0 HRET XCLR PCLK PCTL CLK2 CLK4 YM2 YS2 VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS 1 10 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 10 0.1 GND OSD input HDIN1 VDIN1 CLK1P CLK1N CLK1C CLK2 Parallel data input 0.1 0.1 0.1 To D/A converter CLKOUT HDIN2 CLK3P CLK3N +3.3V CLK3C CLK4 10k 1 GND +3.3V HDPOL1 CLKPOL1 HDPOL2 GND Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 37 - CLKPOL2 VDPOL1 CLKSEL1 CLKSEL2 CLKSEL3 CLKSEL4 VSS CXD2467AQ Package Outline Unit: mm 240PIN QFP(PLASTIC) 34.6 0.2 32.0 0.1 180 181 121 0.10 120 4.1 MAX + 0.10 0.40 - 0.15 A 240 1 0.5 + 0.05 0.22 - 0.03 60 0.08 M 61 + 0.05 0.145 - 0.03 0 - 8 DETAIL A SONY CODE EIAJ CODE JEDEC CODE 0.45 MIN - 0.75 MAX 0.25 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 7.6g LEAD TREATMENT LEAD MATERIAL PACKAGE MASS QFP-240P-L022 QFP240-P-3232 - 38 - |
Price & Availability of CXD2467AQ
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |